Memory is widely used in a wide variety of applications. A typical memory has an array of memory cells arranged in rows and columns, with the memory cells read to or written from by utilizing word lines and bit lines. The bit lines generally link the memory cells within corresponding columns.
One drawback with respect to the bit lines is the potential for coupling to occur between the bit lines of different ports in a multi-port memory. For example, a write operation performed on one port may slow down the read operation on another port. This problem becomes more severe as geometries shrink and the coupling capacitance between wires increases. As a result, there is a need to provide techniques to address bit line coupling.